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Intel Inside Storage Arrays?

Intel Inside Storage Arrays?

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During one of the Intel presentations at the Developer Forum last week the presenter made the statement that Intel processors are deployed in 70%-80%  of storage arrays shipped today.  Initially this may seem like a surprise but on closer inspection, it’s pretty obvious to see that it’s probably an accurate statement.  EMC converted to Xeon technology with VMAX and already used commodity hardware with CLARiiON and now VNX.  Hitachi have moved to Xeon processors with VSP (although they still retain some custom ASICs).  Pretty much every new storage platform being released is based on the Xeon chipset, including the use of Atom processors in SOHO/home NAS devices.

A related conversation took place between Barry Whyte and Nigel Poulton, following Nigel’s post this week on custom ASICs.  Nigel believes custom ASICs will be around for another 5 years, Barry not so.

I have to say I agree with Barry.  We’ve seen commoditisation taking place for some time and companies such as Compellent have based their design on the premise of commodity hardware. Even last week I visited Pure Storage, Nutanix and Solid Fire, all using standard components in their arrays.

One of the subjects of Barry and Nigel’s conversations was 3Par, a company founded in 1999 which released its first products in 2002.  I don’t have any specific information on the first 3Par array design but it’s a good starting point to look back at the processors of that time compared with today.  A quick check at any of the processor benchmark sites shows that processor speeds are 10-20 times faster today than 2000, so implementing thin provisioning and zero block reclaim had to be done in silicon for performance reasons.

With today’s latest Xeon processors that are multi-threaded and multi-core, that’s no longer the case.  The cost and leadtime in developing custom ASICs doesn’t justify their development when the same functionality can be developed in code – code that can be improved and modified on a much faster cycle than designing a new ASIC.

At the last few HP Blogger days it’s been easy to see how HP have acquired and moved products such as LeftHand and Ibrix to their commodity server hardware.  It’s an easy win for HP as they have the hardware base and just need the software IP.  It may seem that 3Par represents more of a challenge but probably not.  HP Labs released their own deduplication technology, so I’m sure they will work out how to implement thin provisioning and zero block reclaim in code.  The hardware is here today to deliver it.

The future is definitely in code and I’d expect HP will drop the custom ASIC within 24 months.  HDS/Hitachi still retain a custom ASIC within their hardware but must be thinking about retiring it soon.  On that subject we should remember HDS have just acquired BlueArc.  The premise of their offering was also custom hardware.  Will HDS choose to retire dedicated silicon from that product line too?  I expect so.

I think in terms of “enterprise” class arrays that leaves us with only the DS8000 series not on Intel Xeon.  I imagine most readers will have their own opinions on that piece of storage legacy storage.  Enough said.

About Chris M Evans

Chris M Evans has worked in the technology industry since 1987, starting as a systems programmer on the IBM mainframe platform, while retaining an interest in storage. After working abroad, he co-founded an Internet-based music distribution company during the .com era, returning to consultancy in the new millennium. In 2009 Chris co-founded Langton Blue Ltd (www.langtonblue.com), a boutique consultancy firm focused on delivering business benefit through efficient technology deployments. Chris writes a popular blog at http://blog.architecting.it, attends many conferences and invitation-only events and can be found providing regular industry contributions through Twitter (@chrismevans) and other social media outlets.
  • http://www.deepstorage.net Howard Marks

    Chris,

    It’s not just compute power but also I/O bandwidth that’s increased. 5 year old Xeons shared an 800Mhz front side bus where today’s Westmeres and Sandy Bridges use a 25GB/s QPI connection to memory and the PCIe bus.

    You should also note that Compellent adds a proprietary cache card to the servers that are their controllers.

    • admin

      Howard, Good point on Compellent’s cache card. I wonder if that will get replaced by a Fusion-IO type “commodity” card over time.

      Chris

  • http://blogs.hds.com/technomusings Michael Hay

    Chris, I think that ASICs, ASSPs, FPGAs, etc. will be around as long as companies can create sufficient value leading to a solid ROI. There is something to be said for special purpose HW be it packaging, ASICs, backplanes, etc. if you have the skills and experiences to actually do it. There is a great post over at Bunnie’s blog (http://bit.ly/qbm8aq) which talks about the potential to return to a day where innovative hardware can beat out the pressure from Moore’s law. I found the read quite interesting. Certainly, Intel is building more function in the microprocessor for storage, but at the same time these are the commodity bits. For instance RAID6 is offloaded to the Intel microprocessor at a time when the industry is rethinking RAID altogether. Does this leave room for a new ASIC that implements some kind of advanced data protection scheme? Potentially. Also Ken Wood and I have done some older and recent posts on this topic (http://bit.ly/npHXlc, http://bit.ly/oAHaC7).

    • admin

      Michael

      Thanks for the reply and the links, which I’ll check out. So, just touching on ROI – do you think custom ASIC design isn’t being done because the ROI/barriers to entry are too great for new startups?

      Chris

  • http://technicaldeepdive.com Nigel Poulton

    Chris,

    Interesting discussion.

    Couple of quick points –

    1. My opinion is that ASICs still have a place in high end enterprise storage, not just storage, specifically high end enterprise. Compellent and the others you mention are not high end enterprise storage.

    2. I take your point about Intel processors since the first 3PAR being 10-20 faster. However, you do not mention that the demands thrown at todays arrays are also hugley up on those from 10 years ago. Todays arrays manage massively more amounts data, have faster front end ports (8Gbps), backend ports (6Gbps), have tiered back ends with SSD on them, as well as having far more and more pwoerful servers attached and throwing more data at them.

    Acheiving all of todays performance and functionality demands in Intel is still a challenge at enterprise scale, pretty sure the guys at Hitachi and 3PAR, who you point out have Intel, didn’t build the ASICs for fun. As you infer, IBM DS8 is not in the same league, and I’ll leave you to make you’re own assumptions about VMAX.

    Will the next 3PAR and VSP have ASICs? May be not, but I stand by my opinion that for the next 5 years in high end enterprise storage, the best technologies will have ASICs.

    Sounds like a great topic for a podcast! If your not out eating Thai curry that is ;-)

  • http://technicaldeepdive.com Nigel Poulton

    Oh Chris, I just saw your comment to Howard about “commodity” Fucion-io.

    Another interesting discussion ;-)

  • http://technicaldeepdive.com Nigel Poulton

    Sorry to keep spamming you tonight Chris but….

    I read the bunniestudios paper that Michael linked to. Very interesting read but I disagree that the trends will lead us back to innovative hardware such as ASICs (of course we’re all speculating massively here).

    IMO, by the time we get to this tipping point where the window for the hardware innvoator becomes larger, we will have lost most of the people who have the skills to innovate and probably much of our capacity to do such (facilities etc). I’m reminded of a steam train project (http://www.a1steam.com) recently done in the UK to build an efficient steam engine compared to diesel. A great project, but fraught with crazy challenges – such as there no longer being any facility in the UK to build a boiler drum large enough to hold the water required for a trip from Newcastle to London and the lack of infrastructure en route to re-fill the train.

    What I personally think is more likely once we hit the plateau (if indeed we ever do), where next years computer is no faster than last years, is start writing more efficient code.

    We all know that a side effect of Intels faster and faster CPU’s is the ability to write lazy sloppy code – uber fast CPUs cover a multitude of coding sins. Once we can no longer deliver faster and faster CPUs, we will start writing better and more efficient code. And by the time we hit that day, all the folks that 30 years ago would have taken the career path of designing custom silicon will be software engineers and writing code for a living. So we’ll have an army of highly skilled coders. I feel like I should make some jab at Enginuity now but will resist.

    One final thought….. I’m also very interested to see how Loongson will effect things Intel going forward.

    Just my penny’s worth.

  • Pingback: Commodity hardware debate heats up again | RayOnStorage Blog

  • http://RayOnStorage.com Ray Lucchesi

    Chris,

    Good post and Michael Hay’s pointer to the “bunnie blog” was almost brillant. However, I disagree with Nigel, the capabilities to do this will be around in a big way for a long time to come.

    A couple of other items I disagreed with which I put into a post on my website at

    Ray

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